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JEDEC JEP156
Chip-Package Interaction Understanding, Identification and Evaluation
| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T18:36:40Z | |
| date available | 2017-09-04T18:36:40Z | |
| date copyright | 03/01/2009 | |
| date issued | 2009 | |
| identifier other | JLROLCAAAAAAAAAA.pdf | |
| identifier uri | http://yse.yabesh.ir/std;jse/handle/yse/218616 | |
| description abstract | This publication references a set of frequently recommended and accepted JEDEC reliability stress tests. These tests are used for qualifying new and modified technology/ process/ product families, as well as individual solid state surface-mount products. | |
| language | English | |
| title | JEDEC JEP156 | num |
| title | Chip-Package Interaction Understanding, Identification and Evaluation | en |
| type | standard | |
| page | 24 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;2009 | |
| contenttype | fulltext | |
| subject keywords | chip-to-package | |
| subject keywords | evaluation | |
| subject keywords | identification | |
| subject keywords | interaction | |
| subject keywords | low-k | |
| subject keywords | ultralow-k |
