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IEEE/IEC International Standard--Format for LSI-Package-Board Interoperable design
IEC 63055:2023-10 (IEEE Std 2401-2019)
| contributor author | IEEE - The Institute of Electrical and Electronics Engineers, Inc. | |
| date accessioned | 2024-12-17T08:08:45Z | |
| date available | 2024-12-17T08:08:45Z | |
| date copyright | 19 October 2023 | |
| date issued | 2023 | |
| identifier other | 10287910.pdf | |
| identifier uri | http://yse.yabesh.ir/std;jse/handle/yse/336272 | |
| description abstract | A method is provided for specifying a common interoperable format for electronic systems design. The format provides a common way to specify information/data about the project management, netlists, components, design rules, and geometries used in the large-scale integration-package-board designs. The method provides the ability to make electronic systems a key consideration early in the design process; design tools can use it to seamlessly exchange information/data. | |
| language | English | |
| publisher | IEEE - The Institute of Electrical and Electronics Engineers, Inc. | |
| title | IEEE/IEC International Standard--Format for LSI-Package-Board Interoperable design | en |
| title | IEC 63055:2023-10 (IEEE Std 2401-2019) | num |
| type | standard | |
| page | 298 | |
| status | Active | |
| tree | IEEE - The Institute of Electrical and Electronics Engineers, Inc.:;2023 | |
| contenttype | fulltext | |
| subject keywords | large-scale integration (LSI) | |
| subject keywords | netlists | |
| subject keywords | design rules | |
| subject keywords | design analysis | |
| subject keywords | packages for LSI circuits | |
| subject keywords | Verilog-HDL | |
| subject keywords | project management | |
| subject keywords | printed circuit board | |
| subject keywords | geometries | |
| subject keywords | common interoperable format | |
| subject keywords | components | |
| subject keywords | IEEE 2401™ | |
| identifier DOI | 10.1109/IEEESTD.2023.10287910 |
