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NASA-LLIS-2041
Lessons Learned – MRO Spaceflight Computer Side Swap Anomalies [Export Version]
Year: 2008
Abstract: Abstract:
A few months into its mission, MRO began experiencing unexpected side swaps to the redundant flight computer that placed the spacecraft into safe mode. The problem was traced to subtle inconsistencies between the MRO design implementation of an ASIC device and a known limitation of that device. Users of the RAD750 spaceflight computer should assure that the "PPCI Erratum 24" ASIC defect cannot cause excessive accumulation of uncorrectable SDRAM memory errors, and that the system architecture has robust error recovery capabilities.
A few months into its mission, MRO began experiencing unexpected side swaps to the redundant flight computer that placed the spacecraft into safe mode. The problem was traced to subtle inconsistencies between the MRO design implementation of an ASIC device and a known limitation of that device. Users of the RAD750 spaceflight computer should assure that the "PPCI Erratum 24" ASIC defect cannot cause excessive accumulation of uncorrectable SDRAM memory errors, and that the system architecture has robust error recovery capabilities.
Subject: 1.Computers
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| contributor author | NASA - National Aeronautics and Space Administration (NASA) | |
| date accessioned | 2017-09-04T18:28:29Z | |
| date available | 2017-09-04T18:28:29Z | |
| date copyright | 39798 | |
| date issued | 2008 | |
| identifier other | IQYCQCAAAAAAAAAA.pdf | |
| identifier uri | http://yse.yabesh.ir/std;jsery=autho146/handle/yse/210693 | |
| description abstract | Abstract: A few months into its mission, MRO began experiencing unexpected side swaps to the redundant flight computer that placed the spacecraft into safe mode. The problem was traced to subtle inconsistencies between the MRO design implementation of an ASIC device and a known limitation of that device. Users of the RAD750 spaceflight computer should assure that the "PPCI Erratum 24" ASIC defect cannot cause excessive accumulation of uncorrectable SDRAM memory errors, and that the system architecture has robust error recovery capabilities. | |
| language | English | |
| title | NASA-LLIS-2041 | num |
| title | Lessons Learned – MRO Spaceflight Computer Side Swap Anomalies [Export Version] | en |
| type | standard | |
| page | 4 | |
| status | Active | |
| tree | NASA - National Aeronautics and Space Administration (NASA):;2008 | |
| contenttype | fulltext | |
| subject keywords | 1.Computers | |
| subject keywords | 1.Engineering design and project processes and standards | |
| subject keywords | 1.Flight Equipment | |
| subject keywords | 1.Flight Operations | |
| subject keywords | 1.Ground Equipment | |
| subject keywords | 1.Hardware | |
| subject keywords | 1.Payloads | |
| subject keywords | 1.Software | |
| subject keywords | 1.Software Engineering | |
| subject keywords | 1.Spacecraft | |
| subject keywords | 1.Spacecraft and Spacecraft Instruments |