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Dielectric Withstanding Voltage (Hipot Method) - Thin Dielectric Layers for Printed Boards

contributor authorIPC - Association Connecting Electronics Industries
date accessioned2017-09-04T16:55:21Z
date available2017-09-04T16:55:21Z
date copyright40118
date issued2009
identifier otherXBCXOCAAAAAAAAAA.pdf
identifier urihttp://yse.yabesh.ir/std;jsery=autho162s7D83081DAC426159DD6EFDEC014A/handle/yse/118831
description abstractThe dielectric withstanding voltage test (Hipot test) consists of the application of a voltage higher than the operating voltage for a specific time across the thickness of the test specimen's dielectric layer. This is used to prove that a printed board can operate safely at its rated voltage and withstand momentary voltage spikes due to switching, surges, and other similar phenomena. Although this test is similar to a voltage breakdown test, it is not intended for this test to cause insulation breakdown. Rather, it serves to determine whether the test specimen's layers have adequate withstanding voltage. This document is applicable to thin dielectric materials such as those defined by IPC-4821. The results can be indicative of a change or a deviation from the normal material characteristics resulting from manufacturing, processing or aging conditions. The test is useful for quality acceptance and in the determination of the suitability of the material for a given application and may be adapted for process control.
languageEnglish
titleIPC TM-650 2.5.7.2Anum
titleDielectric Withstanding Voltage (Hipot Method) - Thin Dielectric Layers for Printed Boardsen
typestandard
page3
statusActive
treeIPC - Association Connecting Electronics Industries:;2009
contenttypefulltext


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