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IEC TR 61189-5-506

contributor authorIEC - International Electrotechnical Commission
date accessioned2020-09-15T22:28:38Z
date available2020-09-15T22:28:38Z
date copyright2019.06.01
date issued2019
identifier otherXJHEIGAAAAAAAAAA.pdf
identifier otherXJHEIGAAAAAAAAAA.pdf
identifier urihttp://yse.yabesh.ir/std;jsessionid=47037D83FC/handle/yse/289076
description abstractScope: This Technical Report is an intercomparison supporting the development of IEC 61189-5-501 in relation to the SIR method. This document sets out to validate the introduction of a new 200-μm gap SIR pattern, and was benched marked against existing SIR gap patterns of 318 μm and 500 μm.
languageEnglish
titleEnglish -- Test methods for electrical materials, printed boards and other interconnection structures and assemblies – Part 5-506: General test methods for materials and assemblies – An intercomparison evaluation to implement the use of fine-pitch test structures for surface insulation resistance (SIR) testing of solder fluxes in accordance with IEC 61189-5-501 - Edition 1.0en
titleIEC TR 61189-5-506num
typestandard
page28
statusActive
treeIEC - International Electrotechnical Commission:;2019
contenttypefulltext


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