JEDEC JESD51-8

Integrated Circuit Thermal Test Method Environmental Conditions - Junction-to-Board

contributor author	JEDEC - Solid State Technology Association
date accessioned	2017-09-04T17:44:51Z
date available	2017-09-04T17:44:51Z
date copyright	36434
date issued	1999
identifier other	EHHBDBAAAAAAAAAA.pdf
identifier uri	http://yse.yabesh.ir/std;jsessioutho9279AF67081DAC4/handle/yse/167905
description abstract	This specification should be used in conjunction with the overview document JESD51, Methodology for the Thermal Measurement of Component Packages (Single Semiconductor Device) [1] and the electrical test procedures described in JESD51-1, 'Integrated Circuit Thermal Measurement Method (Single Semiconductor Device' [2. The environmental conditions described in this document are specifically designed for testing of integrated circuit devices that are mounted on standard test boards with two internal copper planes [3]. This standard is not applicable to packages that have asymmetric heat flow paths to the printed board caused by such thermal enhancements as fused leads (leads connected to the die pad) or power style packages with the exposed heat slug on one side of the package.
language	English
title	JEDEC JESD51-8	num
title	Integrated Circuit Thermal Test Method Environmental Conditions - Junction-to-Board	en
type	standard
page	16
status	Active
tree	JEDEC - Solid State Technology Association:;1999
contenttype	fulltext
subject keywords	Junction-to-Board
subject keywords	Test Method - Environmental Conditions