JEDEC JESD82-15

Standard for Definition of CUA878 PLL Clock Driver for Registered DDR2 DIMM Applications

contributor author	JEDEC - Solid State Technology Association
date accessioned	2017-09-04T17:53:11Z
date available	2017-09-04T17:53:11Z
date copyright	38657
date issued	2005
identifier other	FDTOIBAAAAAAAAAA.pdf
identifier uri	http://yse.yabesh.ir/std;jsessioutho9279AF67081DAC4/handle/yse/176332
description abstract	This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a CUA878 PLL clock device for registered DDR2 DIMM applications. The purpose is to provide a standard for a CUA878 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.
language	English
title	JEDEC JESD82-15	num
title	Standard for Definition of CUA878 PLL Clock Driver for Registered DDR2 DIMM Applications	en
type	standard
page	22
status	Active
tree	JEDEC - Solid State Technology Association:;2005
contenttype	fulltext
subject keywords	CUA878
subject keywords	DDR2
subject keywords	PLL
subject keywords	RDIMM