JEDEC JESD217

Test Methods to Characterize Voiding in Pre-SMT Ball Grid Array Packages

contributor author	JEDEC - Solid State Technology Association
date accessioned	2017-09-04T17:10:20Z
date available	2017-09-04T17:10:20Z
date copyright	09/01/2010
date issued	2010
identifier other	YPMTZCAAAAAAAAAA.pdf
identifier uri	http://yse.yabesh.ir/std;quein=autho123393FD081DAC4/handle/yse/133887
description abstract	This publication provides an overview of solder void types, outlines current metrologies and test methods used for pre-SMPT solder void characterization and potential limitations, and prescribes sampling strategy for data collection, and tolerance guidelines for corrective measures. Test methods can be applied to several types of ball grid array packages such as FCBGA, PBGA, CBGA, and CCGA with minimum 0.5 mm ball-to-ball pitch and constructed with leaded and lead-free solder alloys. Guidelines for pre-SMT voids may not be sufficiently robust where ball grid array packages balls are assembled onto unfilled micro-via structures on package substrate land. Hence, the un-filled microvia construction is considered out-of-scope for this document, while filled via is within scope.
language	English
title	JEDEC JESD217	num
title	Test Methods to Characterize Voiding in Pre-SMT Ball Grid Array Packages	en
type	standard
page	44
status	Active
tree	JEDEC - Solid State Technology Association:;2010
contenttype	fulltext