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JEDEC JESD76
Description of 1.8 V CMOS Logic Devices
| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T17:23:52Z | |
| date available | 2017-09-04T17:23:52Z | |
| date copyright | 04/01/2000 | |
| date issued | 2000 | |
| identifier other | CDSUNAAAAAAAAAAA.pdf | |
| identifier uri | http://yse.yabesh.ir/std;quein=autho123393FD081DAC4/handle/yse/147084 | |
| description abstract | This standard continues the voltage specification migration to the next level beyond the 2.5 V specification already established in JESD80. In this standard, the input and output conditions are described for CMOS Logic products in a 1.8 V (Normal Range) application. | |
| language | English | |
| title | JEDEC JESD76 | num |
| title | Description of 1.8 V CMOS Logic Devices | en |
| type | standard | |
| page | 9 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;2000 | |
| contenttype | fulltext | |
| subject keywords | CMOS Logic Devices - 1.8 V | |
| subject keywords | Low Voltage |
