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JEDEC JESD82-24
Definition of the SSTUB32865 for DDR2 RDIMM Applications 28-bit 1:2 Registered Buffer with Parity
| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T17:33:47Z | |
| date available | 2017-09-04T17:33:47Z | |
| date copyright | 05/01/2007 | |
| date issued | 2007 | |
| identifier other | DDNEACAAAAAAAAAA.pdf | |
| identifier uri | http://yse.yabesh.ir/std;quein=autho123393FD081DAC4/handle/yse/156636 | |
| description abstract | This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUB32865 registered buffer with parity for 2 rank by 4 or similar high-density DDR2 RDIMM applications. The SSTUB32865 is identical in functionality to the SSTU32865 but specifies tighter timing characteristics and a higher application frequency of up to 410MHz. | |
| language | English | |
| title | JEDEC JESD82-24 | num |
| title | Definition of the SSTUB32865 for DDR2 RDIMM Applications 28-bit 1:2 Registered Buffer with Parity | en |
| type | standard | |
| page | 30 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;2007 | |
| contenttype | fulltext | |
| subject keywords | Buffer | |
| subject keywords | DDR2 | |
| subject keywords | RDIMM | |
| subject keywords | Register | |
| subject keywords | SSTU | |
| subject keywords | SSTUB |
