درباره ما
JEDEC JESD51-32
EXTENSION TO JESD51 THERMAL TEST BOARD STANDARDS TO ACCOMMODATE MULTI-CHIP PACKAGES
| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T17:40:59Z | |
| date available | 2017-09-04T17:40:59Z | |
| date copyright | 40513 | |
| date issued | 2010 | |
| identifier other | DWMGFDAAAAAAAAAA.pdf | |
| identifier uri | http://yse.yabesh.ir/std;quein=autho123393FD081DAC4/handle/yse/163889 | |
| description abstract | This document addresses the need for extending the existing thermal test board standards to accommodate the potential of higher electrical connection needs of multi-chip packages (MCPs) and the associated wire routing to implement these connections. The extensions described below also are applicable to single chip packages needing more than 36 electrical connections for the test. | |
| language | English | |
| title | JEDEC JESD51-32 | num |
| title | EXTENSION TO JESD51 THERMAL TEST BOARD STANDARDS TO ACCOMMODATE MULTI-CHIP PACKAGES | en |
| type | standard | |
| page | 10 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;2010 | |
| contenttype | fulltext |
