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JEDEC - Solid State Technology Association: Recent submissions
Now showing items 221-240 of 369
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JEDEC JEP78
Abstract: The intent of this publication is to facilitate the specification of infrared detector diodes, particularly in conjunction with the preparation of data for JEDEC type registration.Subject(s) : Detectors - Infrared , Infrared - Detectors , Spectral Response Curves , -
JEDEC JESD35-A
Abstract: The revised JESD35 is intended for use in the MOS Integrated Circuit manufacturing industry. It describes procedures developed for estimating the overall integrity and reliability of thin gate oxides. Three basic test ...Subject(s) : Thin Dielectrics , Thin Gate Oxides , Wafer-Level Testing , -
JEDEC JESD82-1A
Abstract: This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a CV857 PLL clock device for registered PC1600, PC2100, PC2700 and PC3200 DIMM applications. ...Subject(s) : Clock Driver , CVF857 , dc Interface , DDR , DDR200 , DDR266 , DDR333 , DIMM , PC1600 , PC2100 , PC2700 , PC3200 , PLL , Switching Parameters , -
JEDEC JESD22-B105D
Abstract: This test method provides various tests for determining the integrity lead/package interface and the lead itself when the lead(s) are bent due to faulty board assembly followed by rework of the part for reassembly. For ... -
JEDEC JESD35-1
Abstract: This addendum expands the usefulness of the Standard 35 (JESD35) by detailing the various sources of measurement error that could effect the test results obtained by the ramped tests described in JESD35. Each source of ...Subject(s) : Test Structure - Thin Dielectrics , Thin Dielectrics , Wafer-Level Testing , -
JEDEC JESD4
Abstract: This standard defines reference distances between terminals of the device and the external package at specific voltages.Subject(s) : Clearance Distance , Creepage Distance , Discrete Semiconductor Packages , Rectifier Diodes , Thyristors , -
JEDEC JESD22-A106B
Abstract: This test is conducted to determine the resistance of a part to sudden exposure to extreme changes in temperature and to the effect of alternate exposures to these extremes.Subject(s) : Temperature , Test Method - Thermal Shock , Thermal Shock , -
JEDEC JESD16-A
Abstract: This standard was revised to clarify assumptions necessary to estimate AOQ, revise the minimum sample size algorithm, address small sample size concerns, and provide methods for combining groups for AOQ estimation. Derivation ...Subject(s) : Assessment - Average Outgoing Quality , Average Outgoing Quality , EIA-554 , Parts Per Million (PPM) - Quality Assessment , Quality Levels - Outgoing , -
JEDEC JESD8-8
Abstract: This standard is a result of a major effort by the JC-16 Committee to develop a high performance CMOS-based interface suitable for high speed main memory applications in excess of 125 MHz.Subject(s) : SSTL_3 , Stub Series - Terminated Logic , -
JEDEC JESD471
Abstract: Purpose
It is the purpose of this Standard to provide a distinctive symbol and label to be used to identify those solid state device that require handling. The symbol or label should be used at the lowest practical ... -
JEDEC JESD22-B116A
Abstract: This test provides a means for determining the strength of a gold ball bond to a die bonding surface or an aluminum wedge or stitch bond to a die or package bonding surface, and may be performed on pre-encapsulation or ...Subject(s) : Ball Bond , Test Method - Wire Bond Shear , Wire Bond Shear , -
JEDEC JESD22-A107C
Abstract: Salt atmosphere is a destructive, accelerated stress that simulates the effects of severe seacoast atmosphere on all exposed surfaces. Such stressing and post-stress testing determine the resistance of solid-state devices ... -
JEDEC JESD8-14A.01
Abstract: This new standard provides specifications that will be used by several companies in new 1.0 V products designed in 0.10-0.12 um CMOS technologies, and in components that interface with them. This standard defines power ...Subject(s) : CMOS , CMOS Interface , Digital ICs , Nonterminated , Supply Voltage , -
JEDEC JESD15
Abstract: This document and the associated series of documents are intended to promote the continued development of modeling methods, while providing a coherent framework for their use by defining a common vocabulary to discuss ...Subject(s) : Components , Device , Modeling , overview , Package , Thermal , -
JEDEC JESD22-A118A
Abstract: This test method applies primarily to moisture resistance evaluations and robustness testing, and may be used as an alternative to unbiased autoclave. Samples are subjected to a non-condensing, humid atmosphere, similar ... -
JEDEC JESD5
Abstract: This standard is designed to define voltage-temperature characteristic measurement techniques and a method of calculation. Although many methods could be defined, this method provides a desired uniformity and lends itself ...Subject(s) : Measurement - Temperature Coefficient , Temperature Coefficient - Voltage Regulator Diodes , Voltage Regulator Diodes , -
JEDEC JESD22A121A
Abstract: The methodology presented in this document, see Annex A for process flow, is applicable for studying tin whisker growth from finishes containing a predominance of tin (Sn). This test method may not be sufficient for ... -
JEDEC JESD22-A102D
Abstract: This test method applies primarily to moisture resistance evaluations and robustness testing. Samples are subjected to a condensing, highly humid atmosphere under pressure to force moisture into the package to uncover ... -
JEDEC JESD8-24
Abstract: This document defines the 1.2 V Pseudo Open Drain Interface family of interface standards, POD12, which are generally expected to be implemented with differential amp-based input buffers that, when in singleended mode, ... -
JEDEC JESD73-1
Abstract: This standard covers specifications for a family of 3.3 V NMOS FET bus switch devices. Not included in this document are device specific parameters and performance levels that the vendor must also supply for full device ...Subject(s) : Bus Switch , NFET Switch ,