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JEDEC - Solid State Technology Association: Recent submissions
Now showing items 241-260 of 369
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JEDEC JESD100B.01
Abstract: A revised reference for technical writers and educators, manufacturers, buyers and users of microprocessors, microcomputers, mircocontrollers, memory ICs, and other complex devices. The terms and their definitions in this ...Subject(s) : Memory Integrated Circuits - Symbols , Microcomputers - Symbols , Microprocessors - Symbols , Signal Names , Terms and Definitions - Memory Integrated Circuits , Terms and Definitions - Microcomputers , Terms and Definitions - Microprocessors , -
JEDEC JESD71
Abstract: STAPL is a vendor- and platform-independent language for programming and testing devices via the IEEE standard 1149.1 interface, commonly known as JTAG. STAPL enables programming of designs into programmable logic devices ...Subject(s) : JTAG , Programmable Devices , Programmable Language , STAPL , -
JEDEC J-STD-035
Abstract: This test method defines the procedures for performing acoustic microscopy on nonhermetic encapsulated electronic components. This method provides users with an acoustic microscopy process flow for detecting anomalies ... -
JEDEC JEB5-A
Abstract: The purpose of this bulletin is to recommend for use in the rating of semiconductor logic gating microcircuits which use the binary states to represent and process logic information. Both static and dynamic measurements ...Subject(s) : Logic Gating Microcircuits , Measurement - Static and Dynamic , -
JEDEC JESD22-A105C
Abstract: This test method applies to semiconductor devices that are subjected to temperature excursions and required to power on and off during all temperatures. The power and temperature cycling test is performed to determine the ... -
JEDEC JEP65
Abstract: This publication describes tests which are intended to represent the verification of maximum ratings for data sheets; they are not tests for performance or quality level. This material is to be used in conjunction with ...Subject(s) : Maximum Ratings - Power Transistors , Power Transistors - Maximum Rating Verifications , -
JEDEC JEP170
Abstract: This publ impact en considere products. or visual n in actual p lication prov nd-user produ d visual nonc Finally, it w nonconformit product drawi ides descript cts and/or app conformities s ill depict a m ties and guida ... -
JEDEC JESD229
Abstract: This standard defines the Wide I/O specification, including features, functionality, AC and DC characteristics, packages, and micropillar signal assignments. This standard covers the following technologies: Wide I/O. The ... -
JEDEC JESD74A
Abstract: This standard defines methods for calculating the early life failure rate of a product, using accelerated testing, whose failure rate is constant or decreasing over time. For technologies where there is adequate field ...Subject(s) : Acceleration Factor , Activation Energy , Calculation - ELFR , Early Life - Failure Rate Calculation , Electronic Components , ELFR - Early Life Failure Rate , FIT , -
JEDEC JESD90
Abstract: This document describes an accelerated stress and test methodology for measuring device parameter changes of a single p-channel MOSFET after Negative Bias Temperature Instability (NBTI) stress at dc bias conditions. This ...Subject(s) : MOSFET , NBTI , Negative Bias , P-Channel , PMOS , Temperature , -
JEDEC JESD11
Abstract: This standard indicates the procedures used to convert existing DIP and flat packages for digital parts (SSI & MSI) to chip carrier packages.Subject(s) : Chip Carrier Pinouts , CMOS Devices - 4000 , Logic Circuits - HC and HCT , -
JEDEC JESD73
Abstract: This standard covers specifications for a family of 5 V NMOS FET bus switch devices with 5 V TTL compatible control inputs. Not included in this document are device-specific parameters and performance levels that the vendor ...Subject(s) : Bus Switch , Control Inputs , NMOS FET , TTL Compatible - Control Inputs , -
JEDEC JEP113-B
Abstract: Certain PSMC (Plastic Surface-mount Components) are subject to permanent damage due to moisture-induced failures encountered during high-temperature surface-mount processing unless appropriate precautions are observed. The ...Subject(s) : Labels - Moisture Sensitive , Moisture Sensitive - Symbol and Labels , Symbol - Moisture Sensitive , -
JEDEC JESD84-A43
Abstract: This document is a complete specification for embedded memory devices and removable memory cards using the MMC interface version 4.3. New features developed through the Electrical Joint Task Group include: Sleep mode, Boot ...Subject(s) : 4.3 , boot , Boot Mode , eMMC , Reliable , sleep , Sleep Mode , Write , -
JEDEC JESD353
Abstract: INTRODUCTION
The following noise measurement method applies to transistors whose noise has a Gaussian power distribution, to transistors whose noise has a flat (white) power distribution, and to ... -
JEDEC JESD64-A
Abstract: The purpose is to provide a standard for 2.5 V nominal supply voltage logic devices for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This specification ...Subject(s) : CMOS Logic Devices , Input and Output - CMOS Tolerant , -
JEDEC JESD22-B109A
Abstract: The Flip Chip Tensile Pull Test Method is performed to determine the fracture mode and strength of the solder bump interconnection between the flip chip die and the substrate. It should be used to assess the consistency ...Subject(s) : Chip Pull , Flip Chip , Pb based , Pb-free solder bump , solder bump , Tensile Pull , -
JEDEC JESD313B
Abstract: This standard provides a test method for measuring thermal resistance for conduction cooled power transistors.Subject(s) : Conduction Cooled Power Transistors , Thermal Resistance Measurement - Conduction-Cooled Power , Transistors - Conduction Cooled , -
JEDEC JEP115
Abstract: The purpose of this Test Method is to establish electrical criteria for comparing and specifying power MOSFET performance under high dose rate radiation.Subject(s) : Dose Rate - Power MOSFETs , Power MOSFETs - Dose Rate , Test Method - Dose Rate , Transistors ,