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JEDEC - Solid State Technology Association: Recent submissions
Now showing items 261-280 of 369
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JEDEC JESD52
Abstract: This standard describes dc interface specifications and test environment for these devices that operate with 2.7 V to 3.6 V power supplies. The goal is to provide a consistent set of dc specifications for reference by logic ...Subject(s) : CMOS Logic Devices , Low Voltage - CMOS Devices , TTL Compatible - CMOS Devices , -
JEDEC JESD284A
Abstract: The test methods described in this Standard are generally applicable to alloy-like devices for which the usual simplified equivalent circuits can be employed. Formerly known as EIA-284-A (November 1963). Became JESD284-A ...Subject(s) : Collector-Base Time Constant , Common-Emitter Input , EIA-284 , Test Method - Collector-Base Time Constant , -
JEDEC JESD15-4
Abstract: This guideline specifies the definition and lists acceptable approaches for constructing a compact thermal model (CTM) based on the DELPHI methodology. The purpose of this document is twofold. First, it aims to provide ...Subject(s) : Compact , Component , DELPHI , Device , Modeling , Package , Thermal , -
JEDEC JESD73-3
Abstract: This standard provides a set of uniform data sheet parameters for the description of a single 10-bit, 2.5 V FET transmission-gate bus switch device for DDR memory module and motherboard applications. This bus switch device ...Subject(s) : Bus Switch , DDR , FET , -
JEDEC JESD67
Abstract: This standard attempts to aid in the design of electronic systems comprised of components that operate at several different supply voltages. This document covers respectively configurable I/O voltage, receiver type and ...Subject(s) : Configurable Communication Voltage , I/O Drivers , Impedance , Receiver Type , -
JEDEC JESD60A
Abstract: This method establishes a standard procedure for accelerated testing of the hot-carrier-induced change of a p-channel MOSFET. The objective is to provide a minimum set of measurements so that accurate comparisons can be ...Subject(s) : CHC , DC Stress , Gate Current , Hot Carrier , MOSFETs , P-Channel - MOSFET , PMOS , Transistor , -
JEDEC JESD8-26
Abstract: This standard defines the dc and ac input levels, output levels, and input overshoot and undershoot specifications for the 1.2 V High-speed LVCMOS (HS_LVCMOS) interface. The non-terminated interface has a switching range ... -
JEDEC JESD25
Abstract: This standard provides a test method and definition for small-signal conditions at microwave frequencies.Subject(s) : Measurement - Scattering Parameters , Scattering Parameters , Small Signal Transistors , -
JEDEC JESD306
Abstract: The generator shall have an output impedance of 50 ohms. The attenuator shall be designed to work in a 50 ohm line. The detector and load shall have a 50 ohm input impedance. Network S1 shall be a single-tuned ... -
JEDEC JEB19
Abstract: This recommendation applies to MOS Shift Registers. Definitions are given for P-channel registers but are applicable to all CMOS and N-channel with changes in power supply notation. -
JEDEC JEP162
Abstract: This white paper consolidates industry-wide knowledge and experience on the tools and methods used to address failures of printed circuit boards (PCBs) which occur as a result of IEC 61000-4-2 system-level ESD stressing. ... -
JEDEC JEP155A.01
Abstract: The intent of this report is to document and provide critical information to assess and make decisions on safe ESD level requirements. The scope of this document is to provide this information to quality organizations in ... -
JEDEC JESD51-12
Abstract: This document provides guidelines for both reporting and using electronic package thermal information generated using JEDEC JESD51 standards. By addressing these two areas, this document can be used as the common basis for ...Subject(s) : Electronic Package , Reporting , Thermal , -
JEDEC JESD670A
Abstract: This checklist is intended as a tool to allow users to assess the level of compliance of a quality management system to the requirements ISO 9001:2008. The questions in this checklist are of a generic nature and intended ... -
JEDEC JESD68.01
Abstract: The Common Flash Interface (CFI) specification outlines a device and host system software interrogation handshake that allows specific software algorithms to be used for entire families of devices. This allows device-independent, ...Subject(s) : CFI - Common Flash Interface , Common Flash Interface - CFI , Flash Families , -
JEDEC JESD22-B102E
Abstract: This test method provides optional conditions for preconditioning and soldering for the purpose of assessing the solderability of device package terminations. It provides procedures for dip & look solderability testing of ...Subject(s) : Solderability Testing - Dip and Look , Test Method - Solderability , -
JEDEC JESD209-3
Abstract: This document defines the LPDDR3 specification, including features, functionalities, ACand DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of ... -
JEDEC JESD75-4
Abstract: This standard defines device pinout for 1-, 2- and 3-bit wide logic functions. This pinout specifically applies to the conversion of Dual-Inline-Packaged (DIP) 1-, 2- and 3-bit logic devices to DSBGA-packaged 1-, 2- and ...Subject(s) : Ball Grid Array , BGA , DSBGA , WCSP Logic ,