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JEDEC JEP69-B
Preferred Lead Configurations for Field-Effect Transistors
| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T15:26:09Z | |
| date available | 2017-09-04T15:26:09Z | |
| date copyright | 01/01/1973 (R 1981)(R 1999) | |
| date issued | 1999 | |
| identifier other | NNJTCBAAAAAAAAAA.pdf | |
| identifier uri | http://yse.yabesh.ir/std;quein=autho123393FD081DAC4/handle/yse/26817 | |
| description abstract | This publication indicates preferred pinouts for FETs in various package designs. | |
| language | English | |
| title | JEDEC JEP69-B | num |
| title | Preferred Lead Configurations for Field-Effect Transistors | en |
| type | standard | |
| page | 7 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;1999 | |
| contenttype | fulltext | |
| subject keywords | FETs - Lead Configuration | |
| subject keywords | Lead Configuration - FETs | |
| subject keywords | Transistors - Field-Effect |
