درباره ما
JEDEC JESD8-8
Stub Series Terminated Logic for 3.3 Volts (SSTL-3)
| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T16:20:18Z | |
| date available | 2017-09-04T16:20:18Z | |
| date copyright | 01/01/1996 | |
| date issued | 1996 | |
| identifier other | TKLJCAAAAAAAAAAA.pdf | |
| identifier uri | http://yse.yabesh.ir/std;quein=autho123393FD081DAC4/handle/yse/83726 | |
| description abstract | This standard is a result of a major effort by the JC-16 Committee to develop a high performance CMOS-based interface suitable for high speed main memory applications in excess of 125 MHz. | |
| language | English | |
| title | JEDEC JESD8-8 | num |
| title | Stub Series Terminated Logic for 3.3 Volts (SSTL-3) | en |
| type | standard | |
| page | 19 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;1996 | |
| contenttype | fulltext | |
| subject keywords | SSTL_3 | |
| subject keywords | Stub Series - Terminated Logic |
