JEDEC JESD28-A

Procedure for Measuring N-Channel MOSFET Hot-Carrier-Induced Degradation under DC Stress

contributor author	JEDEC - Solid State Technology Association
date accessioned	2017-09-04T17:13:59Z
date available	2017-09-04T17:13:59Z
date copyright	37226
date issued	2001
identifier other	YZPEUAAAAAAAAAAA.pdf
identifier uri	http://yse.yabesh.ir/std;query=autho162sAF679D/handle/yse/137471
description abstract	This document describes an accelerated test for measuring the hot-carrier-induced degradation of a single n-channel MOSFET using dc bias. The purpose of this document is to specify a minimum set of measurements so that valid comparisons can be made between different technologies, IC processes, and process variations in a simple, consistent and controlled way. The measurements specified should be viewed as a starting point in the characterization and benchmarking of the transistor manufacturing process.
language	English
title	JEDEC JESD28-A	num
title	Procedure for Measuring N-Channel MOSFET Hot-Carrier-Induced Degradation under DC Stress	en
type	standard
page	20
status	Active
tree	JEDEC - Solid State Technology Association:;2001
contenttype	fulltext
subject keywords	DC Stress
subject keywords	Hot Carrier Induced Degradation
subject keywords	N-Channel MOSFET
subject keywords	Test Method - Hot Carrier