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IEEE Standard Testability Method for Embedded Core-based Integrated Circuits
IEEE Std 1500-2022 (Revision of IEEE Std 1500-2005)
| contributor author | IEEE - The Institute of Electrical and Electronics Engineers, Inc. | |
| date accessioned | 2023-08-07T18:46:20Z | |
| date available | 2023-08-07T18:46:20Z | |
| date copyright | 12 October 2022 | |
| date issued | 2022 | |
| identifier other | 9916221.pdf | |
| identifier uri | http://yse.yabesh.ir/std;query=autho162searB46/handle/yse/329560 | |
| description abstract | A mechanism for the test of core designs within a system on chip (SoC) is defined. This mechanism is a hardware architecture and the core test language (CTL) is leveraged to facilitate communication between core designers and core integrators. | |
| language | English | |
| title | IEEE Standard Testability Method for Embedded Core-based Integrated Circuits | en |
| title | IEEE Std 1500-2022 (Revision of IEEE Std 1500-2005) | num |
| type | Standard | |
| page | 168 | |
| tree | IEEE - The Institute of Electrical and Electronics Engineers, Inc.:;2022 | |
| contenttype | Fulltext | |
| subject keywords | test reuse | |
| subject keywords | core test | |
| subject keywords | embedded core test | |
| subject keywords | IEEE 1500 | |
| subject keywords | IP test | |
| identifier DOI | 10.1109/IEEESTD.2022.9916221 |
