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Solderability Tests for Printed Boards

contributor authorIPC - Association Connecting Electronics Industries
date accessioned2017-09-04T16:58:30Z
date available2017-09-04T16:58:30Z
date copyright09/01/2013
date issued2013
identifier otherXJIKGFAAAAAAAAAA.pdf
identifier urihttp://yse.yabesh.ir/std;query=autho18267D83FCDCAC6/handle/yse/121886
description abstractThis standard prescribes test methods, defect definitions, and illustrations for assessing the solderability of printed wiring board surface conductors, attachment lands, and plated-through holes. This standard is intended for use by both vendor and user.
This standard is not intended to verify the potential of successful processing at assembly or to evaluate design impact on wettability. This specification describes procedures or methods to determine the acceptable wettability of a surface finish. Wettability can be affected by handling, finish application, and environmental conditions.
Purpose This standard describes solderability determinations that are made to verify that the printed board fabrication processes and subsequent storage have had no adverse effect on the solderability of those portions of the printed board intended to be soldered. Reference coupons or representative portions of a printed board may be used. Solderability is determined by evaluation of a test specimen which has been processed as part of a panel of boards and subsequently removed for testing per the method selected.
languageEnglish
titleIPC J-STD-003Cnum
titleSolderability Tests for Printed Boardsen
typestandard
page44
statusActive
treeIPC - Association Connecting Electronics Industries:;2013
contenttypefulltext


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