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JEDEC JESD51-3
Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T15:12:05Z | |
| date available | 2017-09-04T15:12:05Z | |
| date copyright | 08/01/1996 | |
| date issued | 1996 | |
| identifier other | AQKZCAAAAAAAAAAA.pdf | |
| identifier uri | http://yse.yabesh.ir/std;query=autho1826AF679D/handle/yse/10512 | |
| description abstract | This standard describes design requirements for a single layer, leaded surface mount integrated circuit package thermal test board. The standard describes board material and geometry requirements, minimum trace lenghts, trace thickness, and routing considerations. Application includes still air and moving air thermal tests. | |
| language | English | |
| title | JEDEC JESD51-3 | num |
| title | Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages | en |
| type | standard | |
| page | 10 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;1996 | |
| contenttype | fulltext | |
| subject keywords | Design Requirements - Leaded Surface Mount | |
| subject keywords | Thermal Test Board |
