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JEDEC JESD75-6
PSO-N/PQFN Pinouts Standardized for 14-, 16-, 20-, and 24-Lead Logic Functions
| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T15:12:44Z | |
| date available | 2017-09-04T15:12:44Z | |
| date copyright | 03/01/2006 | |
| date issued | 2006 | |
| identifier other | LYEZIBAAAAAAAAAA.pdf | |
| identifier uri | http://yse.yabesh.ir/std;query=autho1826AF679D/handle/yse/11281 | |
| description abstract | This standard defines device pinouts for 14-, 16-, 20-, and 24-lead logic functions. This pinout standard specifically applies to the conversion of DIP-packaged logic devices to PSO-N/PQFN packages logic devices. The purpose of this standard is to provide a pinout standard for 14-, 16-, 20-, and 24-lead logic devices offered in 14-, 16-, 20-, and 24-lead PSO-N/PQFN packages for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. | |
| language | English | |
| title | JEDEC JESD75-6 | num |
| title | PSO-N/PQFN Pinouts Standardized for 14-, 16-, 20-, and 24-Lead Logic Functions | en |
| type | standard | |
| page | 12 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;2006 | |
| contenttype | fulltext | |
| subject keywords | Logic Functions | |
| subject keywords | Pinout | |
| subject keywords | PSO-N/PQFN |
