JEDEC JESD82-29A

Definition of the SSTE32882 Registering Clock Driver with Parity and Quad Chip Selects for DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V Applications

contributor author	JEDEC - Solid State Technology Association
date accessioned	2017-09-04T15:14:13Z
date available	2017-09-04T15:14:13Z
date copyright	40513
date issued	2010
identifier other	MCQDRDAAAAAAAAAA.pdf
identifier uri	http://yse.yabesh.ir/std;query=autho1826AF679D/handle/yse/13005
description abstract	This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTE32882 registered buffer with parity for driving address and control nets on DDR3/DDR3L/DDR3U RDIMM applications. The purpose is to provide a standard for the SSTE32882 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. NOTE The designation SSTE32882 refers to the part designation of a series of commercial logic parts common in the industry. This number is normally preceded by a series of manufacturer specific characters to make up a complete part designation.
language	English
title	JEDEC JESD82-29A	num
title	Definition of the SSTE32882 Registering Clock Driver with Parity and Quad Chip Selects for DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V Applications	en
type	standard
page	80
status	Active
tree	JEDEC - Solid State Technology Association:;2010
contenttype	fulltext