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JEDEC JESD82-18A
Standard for Definition of CUA877 and CU2A877 PLL Clock Drivers for for Registered DDR2 DIMM Applications
| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T15:05:23Z | |
| date available | 2017-09-04T15:05:23Z | |
| date copyright | 01/01/2007 | |
| date issued | 2007 | |
| identifier other | LBWRXBAAAAAAAAAA.pdf | |
| identifier uri | http://yse.yabesh.ir/std;query=autho1826AF679D/handle/yse/2839 | |
| description abstract | This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the CUA877 and CU2A877 PLL clock devices for registered DDR2 DIMM applications.The purpose is to provide a standard for the CUA877 and CU2A877 PLL clock devices, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. | |
| language | English | |
| title | JEDEC JESD82-18A | num |
| title | Standard for Definition of CUA877 and CU2A877 PLL Clock Drivers for for Registered DDR2 DIMM Applications | en |
| type | standard | |
| page | 22 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;2007 | |
| contenttype | fulltext | |
| subject keywords | CU2A877 | |
| subject keywords | CUA877 | |
| subject keywords | DDR2 | |
| subject keywords | DIMM | |
| subject keywords | PLL | |
| subject keywords | RDIMM | |
| subject keywords | Zero Delay Buffer |
