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JEDEC JESD82-23
Definition of the SSTUA32S869 and SSTUA32D869 DDR2 RDIMM Applications Registered Buffer with Parity fo
| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T15:05:39Z | |
| date available | 2017-09-04T15:05:39Z | |
| date copyright | 05/01/2007 | |
| date issued | 2007 | |
| identifier other | LCNEACAAAAAAAAAA.pdf | |
| identifier uri | http://yse.yabesh.ir/std;query=autho1826AF679D/handle/yse/3111 | |
| description abstract | This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUA32S869 and SSTUA32D869 registered buffer with parity for driving heavy load on high-density DDR2 RDIMM applications. A typical application would be a 36 SDRAM planar DIMM. The SSTUA32S869 and SSTUA32D869 are identical in functionality to the SSTU32S869 and SSTU32D869 devices respectively but specify tighter timing characteristics and a higher application frequency of up to 410MHz. | |
| language | English | |
| title | JEDEC JESD82-23 | num |
| title | Definition of the SSTUA32S869 and SSTUA32D869 DDR2 RDIMM Applications Registered Buffer with Parity fo | en |
| type | standard | |
| page | 32 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;2007 | |
| contenttype | fulltext | |
| subject keywords | Buffer | |
| subject keywords | DDR2 | |
| subject keywords | Parity | |
| subject keywords | RDIMM | |
| subject keywords | Register | |
| subject keywords | SSTU | |
| subject keywords | SSTUA |
