JEDEC JESD8-26

1.2 V HIGH‐SPEED LVCMOS (HS_LVCMOS) INTERFACE

contributor author	JEDEC - Solid State Technology Association
date accessioned	2017-09-04T15:52:27Z
date available	2017-09-04T15:52:27Z
date copyright	09/01/2011
date issued	2011
identifier other	QNAONEAAAAAAAAAA.pdf
identifier uri	http://yse.yabesh.ir/std;query=autho1826AF679D/handle/yse/55775
description abstract	This standard defines the dc and ac input levels, output levels, and input overshoot and undershoot specifications for the 1.2 V High-speed LVCMOS (HS_LVCMOS) interface. The non-terminated interface has a switching range that is nominally expected to be 0 V to 1.2 V and is primarily intended to support communications with Wide I/O SDRAM devices.
language	English
title	JEDEC JESD8-26	num
title	1.2 V HIGH‐SPEED LVCMOS (HS_LVCMOS) INTERFACE	en
type	standard
page	8
status	Active
tree	JEDEC - Solid State Technology Association:;2011
contenttype	fulltext