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JEDEC JESD22-B109A
Flip Chip Tensile Pull
| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T16:00:33Z | |
| date available | 2017-09-04T16:00:33Z | |
| date copyright | 01/01/2009 | |
| date issued | 2009 | |
| identifier other | RITDLCAAAAAAAAAA.pdf | |
| identifier uri | http://yse.yabesh.ir/std;query=autho1826AF679D/handle/yse/63725 | |
| description abstract | The Flip Chip Tensile Pull Test Method is performed to determine the fracture mode and strength of the solder bump interconnection between the flip chip die and the substrate. It should be used to assess the consistency of the chip join process. This test method is a destructive test. | |
| language | English | |
| title | JEDEC JESD22-B109A | num |
| title | Flip Chip Tensile Pull | en |
| type | standard | |
| page | 16 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;2009 | |
| contenttype | fulltext | |
| subject keywords | Chip Pull | |
| subject keywords | Flip Chip | |
| subject keywords | Pb based | |
| subject keywords | Pb-free solder bump | |
| subject keywords | solder bump | |
| subject keywords | Tensile Pull |
