JEDEC JESD64-A

Standard for Description of 2.5 V CMOS Logic Devices with 3.6 V CMOS Tolerant Inputs and Outputs

contributor author	JEDEC - Solid State Technology Association
date accessioned	2017-09-04T16:01:14Z
date available	2017-09-04T16:01:14Z
date copyright	36800
date issued	2000
identifier other	RKNHCBAAAAAAAAAA.pdf
identifier uri	http://yse.yabesh.ir/std;jsery/handle/yse/64436
description abstract	The purpose is to provide a standard for 2.5 V nominal supply voltage logic devices for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This specification provides for compatibility between devices operating between either the Standard Range of 1.8 V to 2.7 V or the optional Extended Range of 1.65 V to 2.7 V supply voltages, as well as over-voltage tolerance with devices operating at 3.6 V.
language	English
title	JEDEC JESD64-A	num
title	Standard for Description of 2.5 V CMOS Logic Devices with 3.6 V CMOS Tolerant Inputs and Outputs	en
type	standard
page	11
status	Active
tree	JEDEC - Solid State Technology Association:;2000
contenttype	fulltext
subject keywords	CMOS Logic Devices
subject keywords	Input and Output - CMOS Tolerant