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Wide I/O Single Data Rate (Wide I/O SDR)

contributor authorJEDEC - Solid State Technology Association
date accessioned2017-09-04T16:04:16Z
date available2017-09-04T16:04:16Z
date copyright40878
date issued2011
identifier otherRSYQTEAAAAAAAAAA.pdf
identifier urihttp://yse.yabesh.ir/std;query=autho1826AF679D/handle/yse/67634
description abstractThis standard defines the Wide I/O specification, including features, functionality, AC and DC characteristics, packages, and micropillar signal assignments. This standard covers the following technologies: Wide I/O. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant, 1 Gb through 32 Gb SDRAM (monolithic density) devices with 4, 128b wide channels using direct chip-to-chip attach methods between 1 to 4 memory devices and a controller device. This standard was created using aspects of the following standards: DDR2 (JESD79-2), DDR3 (JESD79-3), LPDDR (JESD209), and LPDDR2 (JESD209-2). Each aspect of the standard was considered and approved by committee ballot(s). The accumulation of these ballots was then incorporated to prepare the Wide I/O standard.
languageEnglish
titleJEDEC JESD229num
titleWide I/O Single Data Rate (Wide I/O SDR)en
typestandard
page74
statusActive
treeJEDEC - Solid State Technology Association:;2011
contenttypefulltext


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