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JEDEC JESD22-A105C
Power and Temperature Cycling
| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T16:06:46Z | |
| date available | 2017-09-04T16:06:46Z | |
| date copyright | 01/01/2004 (R 2011) | |
| date issued | 2011 | |
| identifier other | RZJBIEAAAAAAAAAA.pdf | |
| identifier uri | http://yse.yabesh.ir/std;query=autho1826AF679D/handle/yse/69967 | |
| description abstract | This test method applies to semiconductor devices that are subjected to temperature excursions and required to power on and off during all temperatures. The power and temperature cycling test is performed to determine the ability of a device to withstand alternate exposures at high and low temperature extremes with operating biases periodically applied and removed. It is intended to simulate worst case conditions encountered in typical applications. The power and temperature cycling test is considered destructive. It is intended for device qualification. | |
| language | English | |
| title | JEDEC JESD22-A105C | num |
| title | Power and Temperature Cycling | en |
| type | standard | |
| page | 12 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;2011 | |
| contenttype | fulltext |
