JEDEC JESD8-20A
POD15 - 1.5 V Pseudo Open Drain I/O
contributor author | JEDEC - Solid State Technology Association | |
date accessioned | 2017-09-04T15:10:57Z | |
date available | 2017-09-04T15:10:57Z | |
date copyright | 40087 | |
date issued | 2009 | |
identifier other | LSTXOCAAAAAAAAAA.pdf | |
identifier uri | http://yse.yabesh.ir/std;query=autho1826AF679D/handle/yse/9316 | |
description abstract | This standard defines the dc and ac single-ended (data) and differential (clock) operating conditions, I/O impedance, and the termination and calibration scheme for 1.5 V Pseudo Open Drain I/Os. The 1.5 V Pseudo Open Drain interface, also known as POD15, is primarily used to communicate with GDDR4 and GDDR5 SGRAM devices. Item 135.01 | |
language | English | |
title | JEDEC JESD8-20A | num |
title | POD15 - 1.5 V Pseudo Open Drain I/O | en |
type | standard | |
page | 20 | |
status | Active | |
tree | JEDEC - Solid State Technology Association:;2009 | |
contenttype | fulltext | |
subject keywords | 135.01 | |
subject keywords | DRAM | |
subject keywords | GDDR4 | |
subject keywords | GDDR5 | |
subject keywords | Interface | |
subject keywords | Memory | |
subject keywords | POD | |
subject keywords | POD15 | |
subject keywords | POD-15 | |
subject keywords | RAM | |
subject keywords | SGRAM |