JEDEC JESD51-7
High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T15:37:42Z | |
| date available | 2017-09-04T15:37:42Z | |
| date copyright | 02/01/1999 | |
| date issued | 1999 | |
| identifier other | OVTXHAAAAAAAAAAA.pdf | |
| identifier uri | http://yse.yabesh.ir/std;query=autho4703177/handle/yse/39614 | |
| description abstract | This fixturing further defines the environment for thermal test of packaged microelectronic devices. Its function is to provide an alternate mounting surface for the analysis of heat flow in electronic components. The objective of the standard is to provide a high effective thermal conductivity mounting surface that can be compared equally against standard tests done in different laboratories with typical variations of less than or equal to 10%. | |
| language | English | |
| title | JEDEC JESD51-7 | num |
| title | High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages | en |
| type | standard | |
| page | 13 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;1999 | |
| contenttype | fulltext | |
| subject keywords | Analysis - Heat Flow | |
| subject keywords | Test Board - Leaded Surface Mount | |
| subject keywords | Thermal Conductivity |

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