JEDEC JESD82

Definition of CDCV857 PLL Clock Driver for Registered DDR DIMM Applications

contributor author	JEDEC - Solid State Technology Association
date accessioned	2017-09-04T15:38:31Z
date available	2017-09-04T15:38:31Z
date copyright	07/01/2000
date issued	2000
identifier other	OYJZMAAAAAAAAAAA.pdf
identifier uri	http://yse.yabesh.ir/std;query=autho4703177/handle/yse/40586
description abstract	This specification is a reference for Registered DDR DIMM designers. JESD82 defines the physical, electrical, interface and timing requirements of a 1:10 PLL clock driver for DDR Registered DIMMs from DDR200 to DDR266 as refined in revision C of JEDEC Standard 21-C (JESD21-C). JESD82 was also written to meet the future performance requirements of Registered DIMMs for DDR300 and DDR333.
language	English
title	JEDEC JESD82	num
title	Definition of CDCV857 PLL Clock Driver for Registered DDR DIMM Applications	en
type	standard
page	17
status	Active
tree	JEDEC - Solid State Technology Association:;2000
contenttype	fulltext
subject keywords	CDCV857
subject keywords	DDR200
subject keywords	DDR266
subject keywords	DIMM
subject keywords	Double Data Rate - DDR
subject keywords	PLL Clock Driver
subject keywords	Registered DDR DIMM Applications