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JEDEC JESD52
Description of Low Voltage TTL-Compatible CMOS Logic Devices
| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T15:57:31Z | |
| date available | 2017-09-04T15:57:31Z | |
| date copyright | 35004 | |
| date issued | 1995 | |
| identifier other | RAOECAAAAAAAAAAA.pdf | |
| identifier uri | http://yse.yabesh.ir/std;query=autho4703177/handle/yse/60799 | |
| description abstract | This standard describes dc interface specifications and test environment for these devices that operate with 2.7 V to 3.6 V power supplies. The goal is to provide a consistent set of dc specifications for reference by logic suppliers and users alike. | |
| language | English | |
| title | JEDEC JESD52 | num |
| title | Description of Low Voltage TTL-Compatible CMOS Logic Devices | en |
| type | standard | |
| page | 14 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;1995 | |
| contenttype | fulltext | |
| subject keywords | CMOS Logic Devices | |
| subject keywords | Low Voltage - CMOS Devices | |
| subject keywords | TTL Compatible - CMOS Devices |
