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JEDEC JESD82-16A
Definition of the SSTUA32866 1.8 V Configurable Registered Buffer with Parity Test for DDR2 RDIMM Applications
| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T15:08:13Z | |
| date available | 2017-09-04T15:08:13Z | |
| date copyright | 05/01/2007 | |
| date issued | 2007 | |
| identifier other | LKJEACAAAAAAAAAA.pdf | |
| identifier uri | http://yse.yabesh.ir/std;query=autho4703177/handle/yse/6081 | |
| description abstract | This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUA32866 registered buffer with parity test for DDR2 RDIMM applications. The purpose is to provide a standard for the SSTUA32866 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. | |
| language | English | |
| title | JEDEC JESD82-16A | num |
| title | Definition of the SSTUA32866 1.8 V Configurable Registered Buffer with Parity Test for DDR2 RDIMM Applications | en |
| type | standard | |
| page | 44 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;2007 | |
| contenttype | fulltext | |
| subject keywords | DDR2 | |
| subject keywords | RDIMM | |
| subject keywords | Register | |
| subject keywords | Registered Buffer | |
| subject keywords | SSTU | |
| subject keywords | SSTUA32866 |
