JEDEC - Solid State Technology Association

JEDEC JESD234

2017-09-04T18:50:28Z

JEDEC JESD234; TEST STANDARD FOR THE MEASUREMENT OF PROTON RADIATION SINGLE EVENT EFFECTS IN ELECTRONIC DEVICES JEDEC - Solid State Technology Association This test standard defines the requirements and procedures for 40 to 500 MeV proton irradiation of electronic devices for Single Event Effects (SEE), and reporting the results. Protons are capable of causing SEE by both direct and indirect ionization, however, in this energy range, indirect ionization will be the dominant cause of SEE [1-3]. Indirect ionization is produced from secondary particles of proton/material nuclear reactions, where the material is Si or any other element present in the semiconductor. Direct proton ionization is thought to be a minor source of SEE, at these energies. This energy range is also selected to coincide with the commonly used proton facilities, and result in the fewest energy dependent issues during test.
Proton energy is the primary variable in these irradiations: However the energies used in a test do not necessarily reflect the proton spectrum in space. The limits of the test energy range versus the actual environment must be taken into consideration during data analysis. The overall proton SEE rate can sometimes be well characterized by the SEE cross section in the 40-100 MeV range. However, for certain categories of devices an energy dependence in SEE cross-section has been noted. Devices that manifest this energy dependent response are typically those fabricated with heavy metal materials (e.g. tungsten, W, and copper, Cu) residing in close proximity to the sensitive volume and that also exhibit a threshold high enough that the heavy element scattering events are not swamped by more common silicon events. In all cases, the possible secondary reactions are dependent on the incident proton energy.
Proton testing is usually performed in open air with test samples that are not delidded. It is always the experimenter's responsibility to have knowledge of the location of the active die and any overlayers of material (from all sources) which will degrade the raw beam energy, and to make the appropriate adjustments in reporting the results.

JEDEC JEP147

2017-09-04T18:50:04Z

JEDEC JEP147; Procedure for Measuring Input Capacitance Using a Vector Network Analyzer (VNA) JEDEC - Solid State Technology Association This procedure describes a recommended way to measure pin capacitance of devices with SSTL (Stub Series Terminated Logic) interface pins by use of a Vector Network Analyzer. One purpose of this standard procedure is to reduce the lengthy and often inaccurate footnote - usually found around the specification of pin parasitics To a simple reference to this document. In special cases modifying statements may adjust this procedure to the special needs of certain component.

JEDEC JESD22-B106D

2017-09-04T18:49:50Z

JEDEC JESD22-B106D; Resistance to Solder Shock for Through-Hole Mounted Devices JEDEC - Solid State Technology Association

JEDEC JESD24

2017-09-04T18:49:43Z

JEDEC JESD24; Power MOSFET's JEDEC - Solid State Technology Association This standard contains a listing of terms and definitions and letter symbols; a description of established procedures that are followed in the assignment of semiconductor-industry-type designations to power transistors; electrical verification test; thermal characteristics; and a user\'s guide.