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JEDEC JESD8-15A
Stub Series Terminated Logic for 1.8 V (SSTL_18)
| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T16:26:54Z | |
| date available | 2017-09-04T16:26:54Z | |
| date copyright | 09/01/2003 | |
| date issued | 2003 | |
| identifier other | UBQAEBAAAAAAAAAA.pdf | |
| identifier uri | http://yse.yabesh.ir/std;jsessioutho1193177793325273135A68A10958014A0/handle/yse/90095 | |
| description abstract | This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the SSTL_18 logic switching range, nominally 0 V to 1.8 V. The standard may be applied to ICs operating with separate VDD and VDDQ supply voltages. The VDD value is not specified in this standard; however VDD and VDDQ will have the same voltage level in many cases. | |
| language | English | |
| title | JEDEC JESD8-15A | num |
| title | Stub Series Terminated Logic for 1.8 V (SSTL_18) | en |
| type | standard | |
| page | 22 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;2003 | |
| contenttype | fulltext | |
| subject keywords | DDR2 Interface | |
| subject keywords | I/O Interface | |
| subject keywords | SSTL_18 | |
| subject keywords | Stub Series | |
| subject keywords | Terminated Logic |
