TIA J-STD-028

Performance Standard for Construction of Flip Chip and Chip Scale Bumps - IPC/EIA J-STD-028

contributor author	TIA - Telecommunications Industry Association
date accessioned	2017-09-04T18:27:41Z
date available	2017-09-04T18:27:41Z
date copyright	08/01/1999
date issued	1999
identifier other	IOSHKAAAAAAAAAAA.pdf
identifier uri	http://yse.yabesh.ir/std;query=autho47037D83FCDCAC426159DD6E273C9FCD/handle/yse/209896
description abstract	This standard establishes the construction detail requirements for bumps and other terminal structures on flip chips and chip scale carriers. All flip chip and chip scale device terminals shall meet the designated standards detailed in this document which includes such diverse terminations as solder bumps, columns, non-melting stand-offs and conductive polymer deposits. The specific standards for different terminations will therefore be appropriately matched to the particular interconnection. Purpose The purpose of this document is to establish a set of designations and expectations for product performance for the manufacturer and user of flip chip or chip scale devices. Included in this will be the flexibility to implement the best commercial practices and evolving improvements on those practices.
language	English
title	TIA J-STD-028	num
title	Performance Standard for Construction of Flip Chip and Chip Scale Bumps - IPC/EIA J-STD-028	en
type	standard
page	34
status	Active
tree	TIA - Telecommunications Industry Association:;1999
contenttype	fulltext