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Standard Test Methods for Electromechanical Switches (Test Methods for Logic (TTL) Level Endurance and Low Level Endurance) - Addendum 4 to RS-448

contributor authorECIA - Electronic Components Industry Association
date accessioned2017-09-04T16:41:19Z
date available2017-09-04T16:41:19Z
date copyright11/01/1980 (R 1990)
date issued1990
identifier otherVOYHCAAAAAAAAAAA.pdf
identifier urihttp://yse.yabesh.ir/std;query=autho470393FD081D20686159DD6EFDEC9FCD0Facilities%20Engineering%20Command%226EFDEC9FCD/handle/yse/104650
description abstractPURPOSE
The Logic Level Endurance Test is a measure of the ability of a switch to control electrical loads in which the applied voltage exceeds the melting voltage of the switch contact material and is less than the arcing voltage and arcing current. Electronic logic circuits have defined interface signal voltages. Logic "0" is a signal voltage between 0 and 0.9 volts. Logic "1" is a signal voltage greater than 2.4 volts and less than 5.5 volts.
languageEnglish
titleECA RS-448-4num
titleStandard Test Methods for Electromechanical Switches (Test Methods for Logic (TTL) Level Endurance and Low Level Endurance) - Addendum 4 to RS-448en
typestandard
page8
statusActive
treeECIA - Electronic Components Industry Association:;1990
contenttypefulltext


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