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JEDEC JEP162
System Level ESD Part II: Implementation of Effective ESD Robust Designs
| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T15:49:25Z | |
| date available | 2017-09-04T15:49:25Z | |
| date copyright | 01/01/2013 | |
| date issued | 2013 | |
| identifier other | QDWSBFAAAAAAAAAA.pdf | |
| identifier uri | http://yse.yabesh.ir/std;query=authoCA5893FD081D2/handle/yse/52375 | |
| description abstract | This white paper consolidates industry-wide knowledge and experience on the tools and methods used to address failures of printed circuit boards (PCBs) which occur as a result of IEC 61000-4-2 system-level ESD stressing. These include both hard and soft failures, but more emphasis is placed on soft failures from all the observed and anticipated failures and failure scenarios. The methodology is a consistent characterization approach which applies to both IC interfaces and discrete PCB components. | |
| language | English | |
| title | JEDEC JEP162 | num |
| title | System Level ESD Part II: Implementation of Effective ESD Robust Designs | en |
| type | standard | |
| page | 140 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;2013 | |
| contenttype | fulltext |
