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Mechanical Outline Standard for Flip Chip and Chip Size Configurations

contributor authorIPC - Association Connecting Electronics Industries
date accessioned2017-09-04T18:04:44Z
date available2017-09-04T18:04:44Z
date copyright02/01/2003
date issued2003
identifier otherGHPZCBAAAAAAAAAA.pdf
identifier urihttp://yse.yabesh.ir/std;query=authoF237ear369B7AC426159DD6EFDEC9FCD/handle/yse/187634
description abstractThis standard establishes mechanical outline requirements for devices supplied in flip chip or Chip Size Package (CSP) formats, including die surface, die terminals, and interconnection balls/bumps/lands to the next level.
Purpose The purpose of this standard is to establish a family of mechanical outlines and footprints for both the device and the interconnection scheme. Interconnection ball/bump/land size, pitch, configuration, coplanarity, and associated tolerances are included in this standard.
languageEnglish
titleIPC J-STD-027num
titleMechanical Outline Standard for Flip Chip and Chip Size Configurationsen
typestandard
page20
statusActive
treeIPC - Association Connecting Electronics Industries:;2003
contenttypefulltext


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