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JEDEC JESD82-21
Standard for Definition of CUA845 PLL Clock Driver for Registered DDR2 DIMM Applications
| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T16:51:55Z | |
| date available | 2017-09-04T16:51:55Z | |
| date copyright | 01/01/2007 | |
| date issued | 2007 | |
| identifier other | WRVRXBAAAAAAAAAA.pdf | |
| identifier uri | http://yse.yabesh.ir/std;quessionid=2A40ear/handle/yse/115508 | |
| description abstract | This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a CUA845 PLL clock device for registered DDR2 DIMM applications.The purpose is to provide a standard for a CUA845 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. | |
| language | English | |
| title | JEDEC JESD82-21 | num |
| title | Standard for Definition of CUA845 PLL Clock Driver for Registered DDR2 DIMM Applications | en |
| type | standard | |
| page | 22 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;2007 | |
| contenttype | fulltext | |
| subject keywords | CUA845 | |
| subject keywords | DDR2 | |
| subject keywords | DIMM | |
| subject keywords | PLL | |
| subject keywords | RDIMM | |
| subject keywords | SO-CDIMM |
