JEDEC JESD22-B108B

Coplanarity Test for Surface-Mount Semiconductor Devices

contributor author	JEDEC - Solid State Technology Association
date accessioned	2017-09-04T17:07:30Z
date available	2017-09-04T17:07:30Z
date copyright	09/01/2010
date issued	2010
identifier other	YHWTZCAAAAAAAAAA.pdf
identifier uri	http://yse.yabesh.ir/std;quessionid=2A40ear/handle/yse/131040
description abstract	The purpose of this test is to measure the deviation of the terminals (leads or solder balls) from coplanarity at room temperature for surface-mount semiconductor devices. This test method is applicable for inspection and device characterization. If package warpage or coplanarity is to be characterized at reflow soldering temperatures, then JESD22-B112 should be used.
language	English
title	JEDEC JESD22-B108B	num
title	Coplanarity Test for Surface-Mount Semiconductor Devices	en
type	standard
page	14
status	Active
tree	JEDEC - Solid State Technology Association:;2010
contenttype	fulltext