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JEDEC JESD8-9B
Stub Series Terminated Logic for 2.5 Volts (SSTL_2) - ERRATA: October 18, 2002
| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T17:08:59Z | |
| date available | 2017-09-04T17:08:59Z | |
| date copyright | 05/01/2002 | |
| date issued | 2002 | |
| identifier other | YLULABAAAAAAAAAA.pdf | |
| identifier uri | http://yse.yabesh.ir/std;quessionid=2A40ear/handle/yse/132495 | |
| description abstract | This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the SSTL_2 logic switching range, nominally 0 V to 2.5 V. The standard may be applied to ICs operating with separate VDD and VDDQ supply voltages. This standard has been developed particularly with the objective of providing a relatively simple upgrade path from MOS push-pull interface designs. The standard is particularly intended to improve operation in situations where busses must be isolated from relatively large stubs. | |
| language | English | |
| title | JEDEC JESD8-9B | num |
| title | Stub Series Terminated Logic for 2.5 Volts (SSTL_2) - ERRATA: October 18, 2002 | en |
| type | standard | |
| page | 30 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;2002 | |
| contenttype | fulltext | |
| subject keywords | 2.5 V | |
| subject keywords | Logic Switching | |
| subject keywords | Output Drivers | |
| subject keywords | SSTL - SSTL_2 | |
| subject keywords | Stub Series - Terminated Logic | |
| subject keywords | Supply Voltage |
