درباره ما
JEDEC JESD8-2
Standard for Operating Voltages and Interface Levels for Low Voltage Emitter-Coupled Logic (ECL) Integrated Circuits
| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T17:09:02Z | |
| date available | 2017-09-04T17:09:02Z | |
| date copyright | 01/01/1993 | |
| date issued | 1993 | |
| identifier other | YLYUCAAAAAAAAAAA.pdf | |
| identifier uri | http://yse.yabesh.ir/std;quessionid=2A40ear/handle/yse/132559 | |
| description abstract | This Addendum No. 2 to JEDEC Standard No. 8 provides standard operating voltage and interface levels that can be used by designers and application engineers as they develop and introduce new products. Covers the ECL logic family designated 300K ECL. The 300K ECL family is Voltage and Temperature Compensated, with I/O interface levels compatible with the existing 100K ECL and 101K ECl families. | |
| language | English | |
| title | JEDEC JESD8-2 | num |
| title | Standard for Operating Voltages and Interface Levels for Low Voltage Emitter-Coupled Logic (ECL) Integrated Circuits | en |
| type | standard | |
| page | 7 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;1993 | |
| contenttype | fulltext | |
| subject keywords | ECL - Emitter-Coupled Logic | |
| subject keywords | Emitter-Coupled Logic - ECL | |
| subject keywords | Integrated Circuits | |
| subject keywords | Interface Levels - ECL | |
| subject keywords | Operating Voltages - ECL |
