JEDEC JESD35-A

Procedure for the Wafer-Level Testing of Thin Dielectrics

contributor author	JEDEC - Solid State Technology Association
date accessioned	2017-09-04T16:26:05Z
date available	2017-09-04T16:26:05Z
date copyright	04/01/2001
date issued	2001
identifier other	TZJHABAAAAAAAAAA.pdf
identifier uri	http://yse.yabesh.ir/std;quessionid=2A40ear/handle/yse/89323
description abstract	The revised JESD35 is intended for use in the MOS Integrated Circuit manufacturing industry. It describes procedures developed for estimating the overall integrity and reliability of thin gate oxides. Three basic test procedures are described, the Voltage-Ramp (V-Ramp), the Current-Ramp (J-Ramp) and the new Constant Current (Bounded J-Ramp) test. Each test is designed for simplicity, speed and ease of use. The standard has been updated to include breakdown criteria that are more robust in detecting breakdown in thinner gate oxides that may not experience hard thermal breakdown.
language	English
title	JEDEC JESD35-A	num
title	Procedure for the Wafer-Level Testing of Thin Dielectrics	en
type	standard
page	47
status	Active
tree	JEDEC - Solid State Technology Association:;2001
contenttype	fulltext
subject keywords	Thin Dielectrics
subject keywords	Thin Gate Oxides
subject keywords	Wafer-Level Testing