JEDEC JESD8-16A

Bus Interconnect Logic (BIC) for 1.2 Volts

contributor author	JEDEC - Solid State Technology Association
date accessioned	2017-09-04T16:27:58Z
date available	2017-09-04T16:27:58Z
date copyright	38292
date issued	2004
identifier other	UELBKBAAAAAAAAAA.pdf
identifier uri	http://yse.yabesh.ir/std;quessionid=2A40ear/handle/yse/91119
description abstract	This standard defines the electrical parameters for high-speed interfaces for use in the 1.2V electrical environment. Included in the standard are a single ended signaling interface suitable for parallel busses, and a differential signaling interface suitable for clock applications or parallel differential buses. JEDEC BIC Standard JESD8-16A continues the tradition of the JESD8-xx standards, defining electrical interfaces for the industry as new technologies and bus requirements develop. Previously, JEDEC defined standard JESD8-6, the HSTL standard, for use in 1.5V electrical environments. BIC is similar to HSTL, except the power supply voltage has dropped from 1.5V to 1.2V, and interface requirements are tightened to allow much higher speeds.
language	English
title	JEDEC JESD8-16A	num
title	Bus Interconnect Logic (BIC) for 1.2 Volts	en
type	standard
page	26
status	Active
tree	JEDEC - Solid State Technology Association:;2004
contenttype	fulltext
subject keywords	1.2 V
subject keywords	BIC
subject keywords	Bus
subject keywords	Interconnect
subject keywords	Logic
subject keywords	SRAM