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JEDEC JESD82-17
Definition of the SSTUA32S868 and SSTUA32D868 Registered Buffer with Parity for 2R x 4 DDR2 RDIMM Applications
| contributor author | JEDEC - Solid State Technology Association | |
| date accessioned | 2017-09-04T17:15:28Z | |
| date available | 2017-09-04T17:15:28Z | |
| date copyright | 38657 | |
| date issued | 2005 | |
| identifier other | ZDDPIBAAAAAAAAAA.pdf | |
| identifier uri | http://yse.yabesh.ir/std;quessionid=4703-Sta081D206/handle/yse/138845 | |
| description abstract | This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUA32S868 and SSTUA32D868 registered buffer with parity test for DDR2 RDIMM applications. | |
| language | English | |
| title | JEDEC JESD82-17 | num |
| title | Definition of the SSTUA32S868 and SSTUA32D868 Registered Buffer with Parity for 2R x 4 DDR2 RDIMM Applications | en |
| type | standard | |
| page | 32 | |
| status | Active | |
| tree | JEDEC - Solid State Technology Association:;2005 | |
| contenttype | fulltext | |
| subject keywords | DDR2 | |
| subject keywords | DDR2-667 | |
| subject keywords | Parity | |
| subject keywords | RDIMM | |
| subject keywords | Registered Buffer | |
| subject keywords | SSTUA32D868 | |
| subject keywords | SSTUA32S868 | |
| subject keywords | Switching Parameters | |
| subject keywords | Test Loading |
