JEDEC JESD65B

Definition of Skew Specifications for Standard Logic Devices

contributor author	JEDEC - Solid State Technology Association
date accessioned	2017-09-04T16:30:08Z
date available	2017-09-04T16:30:08Z
date copyright	09/01/2003
date issued	2003
identifier other	UKYZDBAAAAAAAAAA.pdf
identifier uri	http://yse.yabesh.ir/std;quessionid=4703-Sta081D206/handle/yse/93443
description abstract	This standard defines skew specifications and skew testing for standard logic devices. The purpose is to provide a standard for specifications to achieve uniformity, multiplicity of sources, elimination of confusion, and ease of device specification and design by users.
language	English
title	JEDEC JESD65B	num
title	Definition of Skew Specifications for Standard Logic Devices	en
type	standard
page	19
status	Active
tree	JEDEC - Solid State Technology Association:;2003
contenttype	fulltext
subject keywords	Clock Driver
subject keywords	Half-period Jitter
subject keywords	Jitter
subject keywords	Lock
subject keywords	PLL
subject keywords	Skew Specification
subject keywords	Static Phase Offset