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IEEE 1164 ERTA
Standard Multivalue Logic System for VHDL Model Interoperability (Std_Logic_1164) - IEEE Computer Society Document
| contributor author | IEEE - The Institute of Electrical and Electronics Engineers, Inc. | |
| date accessioned | 2017-09-04T16:44:46Z | |
| date available | 2017-09-04T16:44:46Z | |
| date copyright | 09/27/1995 | |
| date issued | 1995 | |
| identifier other | VXUOCCAAAAAAAAAA.pdf | |
| identifier uri | https://yse.yabesh.ir/std/handle/yse/108073 | |
| description abstract | This standard is embodied in the Std_logic_1164 package declaration and the semantics of the Std_logic_1164 package body along with this clause 1 documentation. The information annex A is a guide to users and is not part of this standard, but suggests ways in which one might use this package. | |
| language | English | |
| title | IEEE 1164 ERTA | num |
| title | Standard Multivalue Logic System for VHDL Model Interoperability (Std_Logic_1164) - IEEE Computer Society Document | en |
| type | standard | |
| page | 23 | |
| status | Active | |
| tree | IEEE - The Institute of Electrical and Electronics Engineers, Inc.:;1995 | |
| contenttype | fulltext |
