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IEEE 1076.3
Standard VHDL Synthesis Packages - IEEE Computer Society Document
| contributor author | IEEE - The Institute of Electrical and Electronics Engineers, Inc. | |
| date accessioned | 2017-09-04T16:56:22Z | |
| date available | 2017-09-04T16:56:22Z | |
| date copyright | 03/20/1997 | |
| date issued | 1997 | |
| identifier other | XDXKCAAAAAAAAAAA.pdf | |
| identifier uri | https://yse.yabesh.ir/std/handle/yse/119882 | |
| description abstract | This standard defines standard practices for synthesizing binary digital electronic circuits from VHDL source code. It includes the following: a) The hardware interpretation of values belonging to the BIT and BOOLEAN types defined by IEEE Std 1076-1993 and to the STD_ULOGIC type defined by IEEE Std 1164-1993. b) A function (STD_MATCH) that provides "don't care" or "wild card" testing of values based on the STD_ULOGIC type. c) Standard functions for representing sensitivity to the edge of a signal. d) Two packages that define vector types for representing signed and unsigned arithmetic values, and that define arithmetic, shift, and type conversion operations on those types. This standard is designed for use with IEEE Std 1076-1993. Modifications that may be made to the packages for use with the previous edition, IEEE Std 1076-1987, are described in 7.2. | |
| language | English | |
| title | IEEE 1076.3 | num |
| title | Standard VHDL Synthesis Packages - IEEE Computer Society Document | en |
| type | standard | |
| page | 49 | |
| status | Active | |
| tree | IEEE - The Institute of Electrical and Electronics Engineers, Inc.:;1997 | |
| contenttype | fulltext |
